2010 · UC Berkeley
RISC-V
Most instruction sets belong to a company, and you need a license to build a chip that runs them. RISC-V is different: anyone can implement it, for free, for anything. It started as a short university project and ended up in billions of chips.
| Created by | Krste Asanović, Yunsup Lee, Andrew Waterman and David Patterson (UC Berkeley) |
|---|---|
| Started | 2010 |
| Governed by | RISC-V International (a non-profit) |
| License | Open standard, no royalties |
| Base ISA | RV32I: 32-bit, about 40 instructions |
| Registers | x0 to x31, 32 bits each (x0 is always zero), plus PC |
| Instruction length | 32 bits (16-bit compressed forms with the C extension) |
| Common extensions | M (multiply/divide), A (atomics), F and D (floating point), C (compressed), V (vector) |
Why it was built
In 2010 a group at UC Berkeley needed an instruction set for research and teaching. The existing options were either encumbered by licenses, burdened with decades of compatibility baggage, or both. So they designed a fresh one. It was the fifth RISC design to come out of Berkeley, where David Patterson had helped start the RISC movement around 1980, hence the name RISC-V (“risk five”).
They published the specification openly. Companies started using it, and in 2015 a foundation was set up to steward the standard. It is now run by RISC-V International, a non-profit based in Switzerland.
A base plus extensions
RISC-V is not one instruction set but a small base with optional pieces. The base integer set, RV32I, is enough to run a full compiler-generated program on its own. It has about 40 instructions: integer add and subtract, logic, shifts, comparisons, loads and stores of bytes, halfwords and words, branches, jumps, and a few system instructions. Notice what is missing: there is no multiply. That comes with the M extension, so the tiniest chips can leave it out.
Letters stack up: a typical Linux-capable core is “RV64GC”, a 64-bit base plus a general bundle of extensions and compressed instructions.
How RV32I works
There are 32 registers, x0 through x31. Like MIPS, x0 is hardwired to zero, which lets one instruction do many jobs: addi x5, x0, 7 loads a constant, and branching against x0 tests for zero. There are no condition flags at all. Branches compare two registers directly: beq, bne, blt, bge and unsigned versions.
Every base instruction is 32 bits, in one of six formats:
| Format | Used for | Example |
|---|---|---|
| R | Register-to-register arithmetic | add x3, x1, x2 |
| I | Immediates, loads, jalr | lw x5, 8(x2) |
| S | Stores | sw x5, 8(x2) |
| B | Conditional branches | bne x5, x0, loop |
| U | Upper 20-bit immediates | lui x5, 0x12345 |
| J | Jump and link | jal x1, func |
The designers were careful about where bits go. The source and destination register fields sit in the same positions in every format, and the sign bit of every immediate is always the top bit of the instruction. That makes the decoder small and fast, even though some immediates end up with their bits shuffled around. Negative numbers are plain two’s complement throughout.
RISC-V also drops the branch delay slot that MIPS had. The hardware handles pipelining itself, so the instruction set does not have to bake in one particular design.
Why it matters
Because the standard is open, anyone can build a RISC-V core: a student, a startup, or a giant. RISC-V cores now run in storage controllers, microcontrollers such as Espressif’s ESP32-C series, and the Raspberry Pi RP2350, as well as in a growing number of application processors. It is also a natural fit for courses, since RV32I is small enough to build in a semester.
RISC-V in NANDSIM
The museum RISC-V machine is rebuilt from NAND gates and runs real RV32I programs. Open it up to inspect the 32 registers and memory as each instruction goes by.