1985 · MIPS Computer Systems
MIPS
MIPS asked a simple question: what if the CPU only did easy things, but did one of them every clock cycle? The answer ended up in workstations, the PlayStation, the Nintendo 64, countless routers, and nearly every computer architecture course.
| Origin | Stanford University research project led by John Hennessy, from 1981 |
|---|---|
| First commercial chip | R2000, MIPS Computer Systems, 1985 |
| Word size | 32 bits (64-bit versions from 1991) |
| Registers | 32 general-purpose registers ($0 is always zero), HI, LO, PC |
| Instruction length | Fixed 32 bits |
| Formats | 3: R (register), I (immediate), J (jump) |
| Design style | RISC, load/store, five-stage pipeline |
| Famous uses | SGI workstations, PlayStation, Nintendo 64, PlayStation 2, routers |
Why it was built
By 1980, popular processors had grown large instruction sets full of complex operations. Researchers at Stanford, led by John Hennessy, and at Berkeley, led by David Patterson, noticed that compilers rarely used the fancy instructions. Most programs spent their time on simple loads, stores, adds and branches. If a chip did only those, it could do them much faster.
The Stanford project was called MIPS, short for Microprocessor without Interlocked Pipeline Stages. The idea was to keep the hardware so regular that a new instruction could start every cycle, and to let the compiler handle the hard parts. Hennessy co-founded MIPS Computer Systems to sell the idea, and its first chip, the R2000, arrived in 1985.
How it works
MIPS is a load/store machine: arithmetic only happens between registers. Memory is touched only by load and store instructions. There are 32 general registers, each 32 bits. Register $0 always reads as zero, which turns out to be very handy: copying a register is just adding zero to it, and comparing against zero needs no special instruction. Two extra registers, HI and LO, hold the results of multiply and divide.
Every instruction is exactly 32 bits, in one of three formats:
| Format | Fields (bits) | Used for |
|---|---|---|
| R | opcode 6 · rs 5 · rt 5 · rd 5 · shamt 5 · funct 6 | Register arithmetic: add $t0, $t1, $t2 |
| I | opcode 6 · rs 5 · rt 5 · immediate 16 | Constants, loads, stores, branches: lw $t0, 8($sp) |
| J | opcode 6 · address 26 | Jumps: j loop |
Because the register fields sit in the same place in every format, the CPU can read registers before it has even finished working out what the instruction is. That regularity is what makes the pipeline possible.
The five-stage pipeline
The classic MIPS pipeline splits each instruction into five steps: fetch it, decode it and read registers, execute in the ALU, access memory, and write the result back. Like an assembly line, five instructions can be in flight at once, each in a different stage. For the general picture of fetch, decode and execute, see how a CPU works.
Early MIPS chips exposed the pipeline to the programmer. The instruction right after a branch, in the branch delay slot, always runs, and a value loaded from memory was not ready for the very next instruction. Compilers learned to fill those slots with useful work. Later designs kept the branch delay slot for compatibility but stopped requiring the load delay.
Legacy
MIPS chips powered Silicon Graphics workstations, the machines behind much of the 1990s’ computer graphics. The original PlayStation used a MIPS R3000-based CPU, the Nintendo 64 used an NEC chip derived from the R4300i, and the PlayStation 2 and PSP also had MIPS cores. For years MIPS was everywhere in routers and set-top boxes.
It also became the standard teaching architecture through Patterson and Hennessy’s textbook Computer Organization and Design. The two shared the 2017 Turing Award for their work on RISC. In 2021 the company behind MIPS announced it would move to RISC-V, MIPS’s open-standard grandchild.
MIPS in NANDSIM
The museum MIPS is rebuilt from NAND gates and runs real MIPS programs. Open it up to inspect all 32 registers and watch memory change as loads and stores go by.