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Flip-flops, latches and memory: how gates remember

Logic gates have no memory: the same inputs always give the same output. Yet every computer remembers billions of bits. The trick is a loop. Feed a gate’s output back into its own input and the circuit can hold itself in place.

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Feedback: the loop that holds itself up

A circuit made of gates with no loops is called combinational. Its outputs depend only on its current inputs, so it cannot remember anything. Once you allow an output to feed back to an earlier input, the circuit can have more than one stable state for the same inputs, and which one it is in depends on its history. That is memory. Circuits like this are called sequential.

The simplest memory holds one bit with two gates that keep each other in place: if one says 1, the other is pushed to 0, which pushes the first one to stay at 1. Without a nudge from outside, the pair stays put forever (or until the power goes off). How you arrange two NAND gates to do this is one of the nicest puzzles in the game, so we will stop at the idea.

The SR latch

A set–reset latch has two control inputs. A pulse on Set makes the stored bit Q equal 1, and it stays 1 after the pulse ends. A pulse on Reset makes Q equal 0, and it stays 0. With neither input active, the latch simply holds. Asserting both at once is the forbidden case: depending on the design, the outputs end up in a meaningless state or race each other when both inputs are released.

SRQ
An SR latch: Q turns on with the Set pulse and stays on, then turns off with the Reset pulse and stays off.

The very first circuit like this was the Eccles–Jordan trigger, patented in 1918 by the British physicists William Eccles and F. W. Jordan using two vacuum tubes. Circuits with two stable states like this one came to be called flip-flops. Early electronic computers used thousands of them.

The D latch: deciding when to listen

An SR latch needs two signals to say one thing. The D latch takes a single data input, D, and an enable input. While enable is on, Q simply follows D. The latch is transparent. When enable goes off, Q freezes at whatever D was at that moment and ignores D from then on.

The D flip-flop: one instant only

Transparency causes trouble in a clocked machine. If a register’s output feeds back to its own input through some logic, as when a counter adds 1 to itself, a transparent latch would let the value race around the loop many times while the clock is high. The fix is the edge-triggered D flip-flop, which takes in D only at the instant the clock rises from 0 to 1, and holds its output steady the rest of the time. One edge, one step. Compare the two below.

Q 0
DCLKQ
Toggle D and CLK. In flip-flop mode Q only changes when CLK goes from 0 to 1. Switch to latch mode and Q follows D the whole time CLK is 1.
CLKDQ
An edge-triggered D flip-flop samples D only at each rising clock edge (dashed lines). Changes to D between edges are ignored.

Timing: setup, hold and metastability

Real flip-flops need D to be stable for a short time before the clock edge (the setup time) and to stay stable for a short time after it (the hold time). If D changes inside that window, the flip-flop can end up hovering between 0 and 1 for an unpredictable time before it falls one way or the other. This is called metastability. It is why signals arriving from outside a clocked system, such as a button press or data from another chip with its own clock, are usually passed through two flip-flops in a row before they are used. The odds that the first one is still undecided by the time the second samples it are tiny.

From one bit to RAM

Put eight D flip-flops side by side, give them a shared clock and a load control, and you have an 8-bit register. Add a little logic that feeds the register’s output back through an adder and you have a counter, which is the heart of a program counter. Put many registers together with an address decoder that picks which one to write and a selector that picks which one to read, and you have RAM.

Decoderaddress → one lineRegister 0Register 1…Register nSelectoraddress → data out
RAM at block level: the address picks one register to write and one to read. Real RAM chips use much denser cells, but the interface is the same.

Real memory chips don’t build each bit from a full flip-flop. Static RAM (SRAM, used for CPU caches) stores each bit in a loop of two inverters plus two access transistors, six transistors in all. Dynamic RAM (DRAM, your computer’s main memory) stores each bit as charge in a tiny capacitor with one transistor, and has to refresh it thousands of times a second before it leaks away. The idea is the same as the latch: a bit is a physical state that something keeps in place.